IMPLEMENTATION OF AES ALGORITHM ON FPGA AND ON SOFTWARE
Also Available Domains Arithmetic Core|Arithmetic Core|Arithmetic Core
Objective
In this paper we are proposing 128-bit AES algorithm is highly optimized in Key schedule and Sub bytes blocks, for Area and Power. The optimization has been done by reusing the S-box block.
Abstract
Multipliers are the most significant components in the design of many high performance FIR filters, image and digital signal processors in the upcoming digital world. Multipliers being the most area and power consuming elements of a design, area-efficient low-power multiplier architectures are in demand. In this paper, multiplier based on ancient Vedic mathematics technique has been proposed which employs full adders, compressors and other efficient components to achieve the desired parameters for the proposed design.
Combining the Vedic Sutras - urdhva tiryagbhyam sutra and efficient compressors, a robust speed and area efficient multiplier architecture is achieved. The proposed multiplier is designed in Verilog HDL and simulated using Xilinx and Modelsim softwaresNOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Specifications:
Software Requirements:
· Xilinx ISE Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP,
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
Learning Outcomes:
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Concept of Cryptography systems
- Importance of Crypto systems
- Drawbacks of existing methods
- Introduction to Advanced Encryption standard (AES)
- Knowledge on pipelining concept
- Knowledge on Symmetric, Asymmetric and Hash functions
- Applications of AES in real time
- Scope of AES concept in today’s world
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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