HYBRID FULL ADDER CIRCUIT UTILIZING PASS TRANSISTOR AND PFAL ADIABATIC LOGIC STYLE

This paper introduces a groundbreaking hybrid full adder circuit that seamlessly integrates pass transistor logic (PTL) and pulse frequency adiabatic logic (PFAL). The innovative design aims to tackle the pressing challenges of power consumption and speed optimization in digital circuits while maintaining low voltage operation. By leveraging the strengths of both PTL and PFAL techniques, the proposed circuit achieves reduced power consumption through adiabatic switching and improved speed performance compared to traditional CMOS designs. Furthermore, the hybrid approach ensures compatibility with low-voltage applications, addressing a critical need in modern electronics. Through rigorous comparisons with conventional CMOS and PTL implementations, the authors demonstrate substantial improvements in terms of power efficiency and speed, particularly at lower supply voltages. This research contributes significantly to the field of energy-efficient digital circuit design, providing valuable insights into the potential benefits of combining different logic styles to achieve superior overall performance characteristics.