High speed low power multipliers based on reversible logic methods

The focus of this research is to develop multipliers with enhanced characteristics, specifically aiming for higher speed, reduced power consumption, and lower complexity in the lower range. The approach involves leveraging reversible logic, a concept increasingly applied in various fields such as multipliers, low-power CMOS circuits, optical data processing, and quantum circuits.In this study, reversible logic is employed in conjunction with Vedic mathematics Notably, the proposed multipliers utilize established logical principles like the reversible Half Adder, reversible Full Adder, Dual Key Gate, and Kogge Stone Adder. These principles contribute to the efficiency and performance of the multipliers.To ensure superior performance, the research categorizes multiple multipliers based on reversible logic circuits. The designed multipliers are then simulated and synthesized using the Xilinx VIVADO method. The outcomes of these simulations are thoroughly investigated to validate and understand the performance and efficiency of the proposed multiplier designs.

Index Terms: Baugh Wooley Multiplier, Full Adder, Half adder, Reversible Logic, Vedic mathematics