High-Speed Grouping and Decomposition Multiplier for Binary Multiplication

Abstract: The paper presents a novel approach to binary multiplication by introducing a high-speed grouping and decomposition multiplier. The proposed multiplier uses a combination of Wallace tree and Dadda multiplier, and a novel grouping and decomposition technique to reduce the number of partial products and critical path delay. The full adder designed in this is based on GDI Logic. The proposed design is implemented using a 180nm CMOS technology and evaluated against state-of-the-art binary multipliers. The results show that the proposed multiplier outperforms existing designs in terms of speed, power consumption, and area. The design is particularly suitable for use in high-speed digital signal processing applications such as audio and video processing.

Keywords: digital signal processing; fast Fourier transform; grouping and decomposition multiplier; 5:2 logic adder