High-Speed CMOS Synchronous Binary Counter With Constant Counting Rate

This paper presents the design of a high-speed 16-bit synchronous binary counter with a constant counting rate, addressing the limitations of conventional binary counters that experience reduced speed as the bit-width increases. The proposed design incorporates a pre-scaled structure to ensure a consistent counting rate regardless of the counter size. Additionally, an early state detection technique is employed to minimize the critical path delay, accelerating the generation of enable signals for subsequent sub-counters. To further enhance performance, the counter utilizes Johnson counters instead of traditional T-flip-flops, reducing propagation delay and increasing overall speed. This design offers improved performance and scalability, making it suitable for high-speed applications in digital systems, such as frequency dividers, phase-locked loops, and IoT networks.

Index Terms— Binary counter, constant time counter, high-speed counter, pre-scaled counter.