High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic

The Square Root (SQRT) Carry Select Adder (CSLA) architectures include a high-speed design, a design with the lowest area compared to previous CSLAs, and two hybrid designs. The first proposed architecture is an optimized design of the Binary to Excess-1 Converter (BEC)-based CSLA by employing a new fast and merged add-one and multiplexing circuit. This architecture in addition to attaining much lower area, delay, and energy consumption compared to the BEC CSLA, requires almost the same area compared to the best existing CSLA i.e. Irredundant Carry Generation and Selection scheme (IRCGS CSLA) while providing a higher speed. The second proposed CSLA as the lowest-area design is the area-optimized architecture of IRCGS CSLA that exploits a new logic optimization while maintaining its speed. This scheme makes use of multiplexer-based logic to reduce the number of gates and achieve a more compact design. In addition, two hybrid CSLAs are proposed by exploiting the benefits of both proposed CSLA architectures.