In the domain of video processing, edge detection plays a pivotal role in applications such as object recognition, scene understanding, and video surveillance. Real-time video data processing requires efficient hardware architectures capable of handling the computational demands of edge detection algorithms while ensuring low power consumption. This paper introduces a novel VLSI (Very-Large-Scale Integration) architecture designed for real-time video edge detection
In the domain of video processing, edge detection plays a pivotal role in applications such as object recognition, scene understanding, and video surveillance. Real-time video data processing requires efficient hardware architectures capable of handling the computational demands of edge detection algorithms while ensuring low power consumption. This paper introduces a novel VLSI (Very-Large-Scale Integration) architecture designed for real-time video edge detection. The proposed architecture aims to strike a balance between high-performance edge detection and resource-efficient implementation. It utilizes parallel processing and optimized data flow to improve computational speed. Additionally, special attention is given to memory management and data buffering to ensure smooth video stream processing. The architecture is based on Canny edge detection algorithms and is implemented on Artix 7 and Spartan 3E FPGAs. The proposed architecture is also implemented on GPP to validate the performance of the VLSI architecture.
Keywords: Image, Blur, Noise, Restoration, Edge Detection, Canny Detector, Features of image
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