The main objective of this project is to design MAC unit in order to achieve lower power consumption on utilizing the high-speed binary carry select adder.
Multiply-Accumulate (MAC) units have been developed recently for various high-performance applications. A crucial component of computing devices, particularly embedded systems, is the MAC unit. The fundamental MAC unit is composed of Multiplier, Adder, and Accumulator. The input for the MAC unit is read from memory cells and given to the MAC multiplier block that multiplies the inputs and passes the result to an adder, which stores the result in memory. One clock cycle is required to complete the full operation. In this manuscript, a lesser power higher speed MAC unit is proposed for Embedding system. High speed binary carry select adders are utilized in MAC units for their speed and integration with three different blocks includes half sum with carry generators (HSCG), final carry generators (FCG), and final sum generators (FSG). For Multiplier design in MAC unit, the counter-based modular Wallace tree multiplier (CMWTM) is utilized, which has power-saving technique
Keywords:- Multiply-accumulate unit Half sum and carry generator counter-based modular wallace tree multiplier
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Software Requirements:
· Xilinx VIVADO 2023.1
· HDL: Verilog
Minimum Hardware Requirements:
· Microsoft® Windows 7
· Intel® i3 processor or equivalent
· 4 GB RAM
· 250 MB of available disk space
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills