High Performance Multiplier Less Serial Pipelined VLSI Architecture for Real-Valued FFT

This paper presents a high-performance multiplier less serial pipelined design for real-valued fast Fourier transform (FFT). a new data mapping scheme (DMS) is usually recommended for the proposed serial pipelined FFT design. The performance is increased by performing FFT computations in log2N−1 stages followed by a select-store-feedback (SSF) stage, where N is that the number of points in FFT. Additional improvement in performance is achieved by using quarter-complex multiplier fewer units created from memory and combinational logic in each stage. The memory stores half number of partial products whereas the remaining partial products are taken care by external combinational logic. Compared with the best existing theme, the proposed design reduces the computational employment on half-butterfly (H-BF) units by (2N − 8). Application specific integrated circuit (ASIC) and field programmable gate array (FPGA) results show that the proposed design for 1024-point achieves less area, less power, less areadelay product (ADP), less sliced look-up tables (SLUTs) and less flip-flops (FFs) as compared to the most effective existing scheme.