High Performance Filter Design using Adders and Multipliers
Also Available Domains Arithmetic Core
Objective
The main aim of this work is to design a novel Filter which is used in DSP applications. In this project,a high speed FIR filter was designed by using parallel prefix adder and mutiplier.
Abstract
A digital filter is a basic building block in any digital signal processing (DSP) system. A basic filter consists of a delay element, adder and a multiplier. In this paper, FIR filter is designed using kogge stone adder to enhance the Performance of FIR filter which is critical in DSP Applications. The simulation results presented show that the proposed FIR Filter has better performance compared to the existing Filter that employed carry save adder.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx ISE Tool
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Introduction to FIR Filters
- Different types of adders
- Kogge stone adder
- Carry save adder
- Advantages of Kogge stone adder
- How to design High speed, Low power and Area Efficient Circuits
- Scope in today’s world
- Applications in real time
- Xilinx ISE for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
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