High Performance Architecture for Flow-Table Lookup in SDN on FPGA
Also Available Domains Communications and Crypto Core
Objective
The main objective of this paper is to achieve high throughput and low latency by using Range-based Ternary Search Tree (RTST) for providing a fast lookup flow. This RTST can be implemented with parallel multi-pipeline architecture for improving the performance of lookup
Abstract
Range-based Ternary Search Tree (RTST), a tree-based approach for flow-table lookup in SDN network is proposed in this project. RTST builds upon flow-tables in SDN switches to provide a fast lookup among flows. We present a parallel multi-pipeline architecture for implementing RTST that benefits from high throughput and low latency.
The proposed RTST and architecture achieve a memory efficiency of 1 byte of memory for each byte of flow. We also present a set of techniques to support dynamic updates. Experimental results show that RTST can be used to improve the performance of flow-lookup.
The effectiveness of the proposed method is synthesized and simulated using Xilinx Vivado.
Keywords: Software-Defined Networking (SDN), flow-table, Range-based Ternary Search Tree (RTST), Field-Programmable Gate Array (FPGA)
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Block Diagram
Specifications
Software Requirements:
- Xilinx Vivado
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Paper Publishing
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