High Performance Architecture for Flow-Table Lookup in SDN on FPGA

Also Available Domains Communications and Crypto Core

Project Code :TVPGTO400

Objective

The main objective of this paper is to achieve high throughput and low latency by using Range-based Ternary Search Tree (RTST) for providing a fast lookup flow. This RTST can be implemented with parallel multi-pipeline architecture for improving the performance of lookup

Abstract

Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and Pseudo Random Bit Generator (PRBG) algorithms and also used in many applications. Carry Save Adder (CS3A) is the widely used technique to perform the three-operand addition.

In carry save adder at final stage uses ripple carry adder which will cause large critical path delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson Adder (HCA) can also be used for three-operand addition that significantly reduces the critical path delay with more area complexity.

Hence, a new high-speed and area-efficient adder architecture is proposed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area and less delay. The effectiveness of the proposed method is designed using Xilinx ISE 14.7

Keywords: Arithmetic Circuits, Three-operand adder, Carry Save Adder (CSA), Han-Carlson Adder (HCA)

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