High Efficient GDI-CNTFET-Based Approximate Full Adder for Next-Generation of Computer Architectures

Also Available Domains H-Spice

Project Code :TVMABE200

Objective

The main objective of this paper is to present approximate full adder with low error and complexity.

Abstract

In this paper, an approximate full adder is proposed. This structure is based on GDI- CNTFET configuration. It is well known that GDI and CNTFET are belongs to low power techniques. And these are the advanced technologies of CMOS Logic. This design is simulated using H-spice employing respective library files.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Specifications:

Software Requirements:

· H-spice

· Technology files: 32nm

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Demo Video

Request Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice