High-Bandwidth Spatial Equalization for mm Wave Massive MU-MIMO with Processing-in-Memory

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVPGFE101

Objective

The main objective of this project is to reduce the silicon area and power. In these two different finite-alphabet equalization hardware implementations that tightly integrate the memory and processing elements by a parallel array of multiply-accumulate (MAC) units and it-serial processing-in-memory (PIM) architecture

Abstract

In this project, we explore two different finite-alphabet equalization hardware implementations that tightly integrate the memory and processing elements: (i) a parallel array of Multiply-Accumulate (MAC) units and (ii) a bit-serial Processing In Memory (PIM) architecture.

It is able to address both of these issues by using equalization matrices that contain low-resolution entries to lower the power and complexity of high-throughput matrix-vector products in hardware Our all-digital VLSI implementation results show that the bit-serial PIM architecture reduces the area and power consumption, when compared to a parallel MAC array that operates at the same throughput.

Keywords: Millimetre Wave (mmWave), massive multi-user MIMO, spatial equalization, quantization, Processing-In-Memory (PIM).

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7/Xilinx Vivado
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Combinational & Sequential circuits
About MIMO
Knowledge on MAC unit
About Processing Element
Knowledge on Arithmetic and Logic Unit
Content Addressable Memory (CAM)
Knowledge on Memory elements
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing