The main objective of this project is to reduce the voltage harmonics generated by ASD using DVR along with the mitigation of different PQD occurs at PCC .
In this project, to mitigate harmonics generated by nonlinear critical loads, a novel topology is proposed. Because the harmonics generated by non-linear critical loads are the industry's main concern. A Dynamic Voltage Restorer (DVR) control technique is defined to restrict the voltage harmonics introduced by the utility's Adjustable Speed Drive (ASD). In addition, this control technique preserves the steady ASD DC-link voltage during any PCC disturbances.
The dq0 frame shows the mathematical explanation for limiting ASD voltage harmonics and producing reference DC-link ASD voltage. The transistor-clamped Multilevel Inverter (MLI) H-bridge (TCHB) is used as a DVR voltage source inverter.
An improved capacitor voltage balancing (ECVB) technique for the fast dynamic output of DVR for TCHB MLI is also discussed. Using MATLAB program, the suggested DVR control technique to reduce ASD voltage harmonics is simulated.
Keywords: Drives, Power quality, Harmonics, Dynamic voltage restorer, Multi-level inverter, Capacitor voltage balancing.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Software Configuration:
Operating System : Windows 7/8/10
Application Software : Matlab/Simulink
Hardware Configuration:
RAM : 8 GB / 4 GB (Min)
Processor : I3 / I5(Mostly prefer)