FPGA-Supported HDL Approach to Implement Reversible Logic Gate-Based ALU

This manuscript banks on the design of reversible gates and implementation of an Arithmetic Logic Unit – 16 bit (ALU) utilizing Verilog with Xilinx ISE 14.7, Spartan 6 FPGA kit. The same functionality is compared with a basic logic gate-based ALU. Reversible gates can produce a distinct output vector from each input vector, and the opposite is also possible. Circuits with irreversible gates suffer from data erosion. Power loss results from a circuit's loss of data. In conclusion, gates with reversible logic are preferable over irreversible counterparts. A library of reversible gates, comprising of AND, OR, NAND, NOR, and XOR, using Verification Logic Hardware Description Language (HDL) is developed, which in turn contributes to the designing of arithmetic and combinational logic like full adder, decoder (2:4), decoder (3:8), multiplier, full subtractor, and comparator

Keywords : Reversible Logic Gates, Verilog, Xilinx ISE.