FPGA Implementation of Vedic Floating Point Multiplier

Project Code :TVMAFE178

Objective

An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers.

Abstract

Most of the scientific operation involve floating point computations. It is necessary to implement faster multipliers occupying less area and consuming less power. Multipliers play a critical role in any digital design. Even though various multiplication algorithms have been in use, the performance of Vedic multipliers has not drawn a wider attention. Vedic mathematics involves application of 16 sutras or algorithms. One among these, the Urdhva tiryakbhyam sutra for multiplication has been considered in this work. An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers. Xilinx FPGA has been made use of while implementing these algorithms and a resource utilization and timing performance based comparison has also been made.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Specifications

Hardware requirement

             Processor               -    Pentium –III

 

Speed                                -    1.1 GHz

RAM                                 -    1 GB (min)

Hard Disk                          -   40 GB

Floppy Drive                     -    1.44 MB

Key Board                         -    Standard Windows Keyboard

Mouse                                -    Two or Three Button Mouse

Monitor                              -    SVGA

 

Software requirements

Operating System            :Windows95/98/2000/XP/Windows7

 

Front End                          :   Modelsim 6.3 for Debugging and Xilinx 14.3 for                     Synthesis and Hard Ware Implementation

 

This software’s where Verilog source code can be used for design implementation.

 

 

Learning Outcomes

  • Basics of Digital Electronics
  • VLSI design Flow
  • Introduction to Vedic multiplier
  • Writing Verilog code.
  • Introduction to floating point
  • Knowledge on FPGA implementation
  • Applications in real time

·         Xilinx tool for writing code, synthesis and simulation

·         Solution providing for real time problems

·         Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills

o   Debugging Skills

o   Presentation Skills

o   Thesis Writing Skills

 

 

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