Also Available Domains Arithmetic Core|Xilinx Vivado|Xilinx ISE
High performance Finite Impulse Response (FIR) filters are extensively used in digital signal processing (DSP), communications, image processing and many more areas. This paper approaches Field Programmable Gate Arrays (FPGAs) based on systolic FIR architectures using multi-channel technique with symmetric coefficients to ensure faster response and optimum area. The embedded Digital Signal Processing (DSP) blocks for its multiply-accumulator (MAC) perform accurate operations where the filter architecture is efficiently realized in the reconfigurable hardware platform. The characteristics of systolic FIR architecture are synchrony, modularity and regularity to make a perfect filter design. Also its pipeline structure provides high throughput and symmetric technique reduces the memory size. Both of these techniques improve the overall performance of the FIR architecture in FPGA domain
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Software Requirements:
· Xilinx ISE Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP,
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills