FPGA Implementation of Single Precision Floating Point Multiplier using High Speed Compressors
Also Available Domains Arithmetic Core|Xilinx ISE
Abstract
One of the most important considerations in every digital system is the floating point multiplier. In this work, a High Speed Single Precision Binary Floating Point Multiplier is implemented using the IEEE 754 standard and the concepts of High Speed Compressors. The usage of these compressors makes the multiplier faster than a typical multiplier since they are a unique form of adder that can add a greater number of bits at a time. Using these compressors, a 2424 bit multiplier for Mantissa calculations has been created.
The proposed multiplier gets a maximum frequency of 1467.136MHz thanks to these high speed compressors. It is designed for the Xilinx Virtex-5 FPGA and implemented using Verilog HDL.
Keywords- Compressors, Floating point multiplier, Mantissa,
IEEE754 standard, Verilog HDL.
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Block Diagram
Specifications
Hardware requirement
Processor - Pentium –III
Speed - 1.1 GHz
RAM - 1 GB (min)
Hard Disk - 40 GB
Floppy Drive - 1.44 MB
Key Board - Standard Windows Keyboard
Mouse - Two or Three Button Mouse
Monitor - SVGA
Software requirements
v Operating System :Windows95/98/2000/XP/Windows7
v Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation
v This software’s where Verilog source code can be used for design implementation.
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to FPGA
- Writing Verilog code.
- Introduction to Combinational circuits.
- Knowledge on single precision floating point.
- Applications in real time
· Xilinx tool for writing code, synthesis and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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