Also Available Domains DSP Core|Xilinx ISE
Field programmable gate array (FPGA) is
widely used for efficient hardware realization of digital signal processing (DSP)
circuits and systems. Finite impulse response (FIR) filter is
the core of any DSP and communication
systems. To improve the performance of FIR filter, an efficient multiplier is
required. Wallace tree and Vedic multipliers are used in this paper for the
implementation of sequential and
parallel micro programmed FIR filter architectures. The designs are realized
using Xilinx Virtex-5 FPGA. FPGA implementation results are presented and
analyzed. Based on the implementation
results, sequential FIR filter using Wallace tree multiplier/carry skip adder
combination proves to be more efficient as compared to other multiplier/adder
combinations.
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Speed - 1.1 GHz
RAM - 1 GB (min)
Hard Disk - 40 GB
Floppy Drive - 1.44 MB
Key Board - Standard Windows Keyboard
Mouse - Two or Three Button Mouse
Monitor - SVGA
Software requirements
v Operating System :Windows95/98/2000/XP/Windows7
v Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation
v This software’s where Verilog source code can be used for design implementation.
· Xilinx tool for writing code, synthesis and simulation
· Solution providing for real time problems
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