FPGA Implementation of Radix-2 based FFT Architecture for Real-Valued signal processing

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE406

Objective

The main aim of this paper is to reduce complexity and improve the performance. We are implementing based on optimized paths for radix 2^2, 2^3 and 4 parallel implementations.

Abstract

In this project, various pipelined FFT architectures have been proposed. It maximizes the utilization of hardware resource and reduces the number of adders. It requires less area and achieves high throughput and low latency by tradeoff with accuracy. For higher values of N, the FFT (Fast Fourier Transform) architecture has many butterfly structures which has been optimized. In this project 2-Parallel Radix-2^2 Architecture for two different designs have been proposed. A 4-Parallel Radix-2 architecture FFT has also been implemented. By using these implemented designs various parameters such as area and delay variations are observed.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx Vivado Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Fourier Transform
Knowledge on Discrete Fourier Transform and Fast Fourier Transform
Different architecture for FFT implementation
Knowledge on radix-2 butterfly
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice