FPGA Implementation of Efficient and Low Power Test Pattern Generator

Given the multiple challenges posed by testing VLSI circuits in terms of space overhead, power, and speed, the VLSI circuits must be put to the test. Generations of Low Power LFSR test patterns are one method for testing a complicated architecture of VLSI Circuits. VLSI circuits need to be tested both before and after construction, just like other electronic components do. A 32-bit Low Power-LFSR (LP-LFSR) is suggested in this paper as a means of evaluating the VLSI design. The standard LFSR and an extra combinational network are used in the construction of this 32-bit test pattern generator to achieve minimal power consumption. Using VIVADO version 2018, the LP-LFSR's design and verification were completed in Verilog HDL. Because there is less switching between the test vectors, there is less power usage. 16 mW of electricity is produced by the test pattern generator design. The production of 32-bit test patterns requires a high level of switching activity, which is improved in this research. The experimental findings demonstrate that a low power linear feedback shift register has a dynamic power that is 67.34 percent lower than a conventional LFSR.