FPGA Implementation of DC Bias Removal Filters – A Case Study with an ECG Signal
Also Available Domains Xilinx Vivado|Xilinx ISE
Abstract
In this project, we are studying and processing the bio-signals and the perception of clinical images is an important part of modern medical science, technology and engineering. In each registered electrocardiogram (ECG) data, there are two major noise sources such as the power-line interface and baseline wandering noise. A low-frequency noise of about 0.5 to 0.6 Hz is the second, i.e. the baseline wander (closer to a dc). This wandering baseline is practically due to inadequate skin sensitivity to electrodes, i.e. due to relaxed interaction with electrodes or poor positioning or even tightly positioned electrodes. To suppress the DC offset, the conventional DC bias removal filter and its three variants are used in this study. Finally, the simulation results of device utilization, clock speed, and power dissipation are compared among all the designs.
Keywords: DC bias removal; FPGA, filtering; performance;
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx ISE/Xilinx Vivado Tool
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP,
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Concept of DC bias removal filters
- Importance of filters
- Drawbacks of conventional baseline wandering noise removal from an ECG signal
- Introduction to DC filters
- Knowledge on various types of filters
- Study on ECG signal processing
- Applications of DC bias removal filters in real time applications
- Scope of filters concept in today’s world
- Applications in real time
- Xilinx ISE 14.7/Xilinx Vivado for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Paper Publishing
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