FPGA Implementation of Coupled Variable Input Linear Congruential Generator (LCG) Method and Its VLSI Architecture for Pseudorandom Bit Generation

The objective of this work is to design and implement a Coupled Variable Input Linear Congruential Generator (LCG) on FPGA for high-quality pseudorandom bit generation and to develop its corresponding VLSI architecture optimized for speed, area, and power efficiency. The proposed design aims to enhance randomness characteristics by coupling variable inputs within the LCG structure, thereby improving statistical properties over conventional LCGs. The architecture is described using Verilog HDL, synthesized, and implemented on an FPGA platform, with performance evaluated through hardware metrics and standard randomness tests, demonstrating its suitability for cryptographic, security, and stochastic computing applications.