FPGA Implementation of 32-Bit MAC Unit Using Vedic Multiplier and Carry Save Adder

This project is to design and implement a 32-bit Multiply–Accumulate (MAC) unit on FPGA using a Vedic multiplier and a Carry Save Adder (CSA) to achieve high-speed and area-efficient arithmetic operations. The work aims to exploit the parallelism of Vedic multiplication for faster partial product generation while using CSA to reduce accumulation delay in successive operations. The proposed MAC unit is described in Verilog HDL, synthesized, and implemented on an FPGA platform to evaluate performance in terms of area utilization, delay, power consumption, and throughput, demonstrating its suitability for high-performance digital signal processing and AI-oriented applications.