FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k FFT

Also Available Domains DSP Core|Xilinx ISE|Xilinx Vivado

Project Code :TVPGFE115

Objective

The aim of this project is to implement a new butterfly processing element (BPE) where the concept of the radix-r butterfly computation in FFT which is used in many signal processing applications. Through this proposed structure, the delay will be reduced

Abstract

In this project, we propose multiplexed and pipelined building blocks of higher radix-2k FFT. The advantage of using higher radix is the number of multiplications and the number of stages to execute an FFT decrease. The appearance of the radix 2^2 is a milestone in the design of pipelined FFT architectures. Later, radix-2^2 was extended to radix-2k.

This proposed implementation in this project is the Butterfly Processing Elements (BPE) where the concept BPE the butterfly calculation of the radix-r was implemented as the Combination of parallel alpha radix-2 butterflies that will reduce the resources.

An efficient FFT implementation is feasible using our proposed multiplexed and pipelined BPE. The difference between radix-2^2 and radix-2k is the position of twiddle factor is changed, which will reduce the number of complex multiplications and additions because of this the reduction in resources is occurred.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Demo Video

Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing