FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k FFT

Also Available Domains DSP Core|Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE92

Objective

The aim of this project is to implement a new butterfly processing element (BPE) where the concept of the radix-r butterfly computation in FFT which is used in many signal processing applications. Through this proposed structure, the delay will be reduced

Abstract

In this project, we propose multiplexed and pipelined building blocks of higher radix-2k FFT. The advantage of using higher radix is the number of multiplications and the number of stages to execute an FFT decrease. The appearance of the radix 2^2 is a milestone in the design of pipelined FFT architectures. Later, radix-2^2 was extended to radix-2k.

This proposed implementation in this project is the Butterfly Processing Elements (BPE) where the concept BPE the butterfly calculation of the radix-r was implemented as the Combination of parallel alpha radix-2 butterflies that will reduce the resources.

An efficient FFT implementation is feasible using our proposed multiplexed and pipelined BPE. The difference between radix-2^2 and radix-2k is the position of twiddle factor is changed, which will reduce the number of complex multiplications and additions because of this the reduction in resources is occurred.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7/Xilinx Vivado
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding.
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Distributed Arithmetic Circuits
Multiplier based approaches for Radix FFT
Drawbacks of based approaches for Radix FFT
How to achieve high speed, Low power and Area efficiency?
Introduction Multiplier Less based approaches for Radix FFT
Advantages of using Multiplier Less based approaches for Radix FFT
Scope of approximation concept in today’s world
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice