FPGA based UART Design: Simulation, Synthesis & System Verilog functional verification

Project Code :TVMAFE707

Objective

Implement a UART (Universal Asynchronous Receiver/Transmitter) on FPGA • Design a UART transmitter (TX) and receiver (RX) module in HDL (SystemVerilog or Verilog), so that serial communication (asynchronous) can be achieved. • Provide configurable parameters for UART, like baud rate, data bits, parity, and stop bits. (Many designs include a baud-rate generator.) • Use FPGA hardware (e.g., a Xilinx or Intel/Altera board) to demonstrate real, physical serial communication

Abstract

Abstract: The UART is a communication protocol that operates on serial data transmission (sending information bit-by-bit) between different modules asynchronously. As the number of devices increases, multi-UART is used to communicate between them by selecting desired baud rates. This paper discusses the design, verification & implementation of multi-UART on Nexys 4 DDR FPGA board. The verification environment is created on Questa Sim software using System Verilog assertions and functional coverage to verify the correctness and effectiveness of design. The design was simulated on Xilinx Vivado software and the resulting simulation waveform is analyzed to verify the functionality of the design. The resultant waveform illustrates the multi-UART has tendency to transfer data with minimum latency, fulfilling with timing constraints. The design of this paper built a strong solution for multi-UART data communication offering a effective foundation for future improvements in communication protocols

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