FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications

Project Code :TVMATO1157

Objective

This paper presents approximate multipliers which are efficiently deployed on Field Programmable Gate Arrays (FPGAs) by using newly proposed approximate logic compressors at different levels of accuracy.

Abstract

ABSTRACT: This paper presents approximate multipliers which are efficiently deployed on Field Programmable Gate Arrays (FPGAs) by using newly proposed approximate logic compressors at different levels of accuracy. Our approximate multiplier designs offer higher gains of power-delay-area products (PDAP) than those of the state-of-the-art works at comparable accuracies. Furthermore, in terms of delay, occupied area, and dynamic power dissipation, our designs are much better than Lookup Table based multiplier Intellectual Properties that are available on an FPGA. Particularly, our proposed 8-, 16-, and 32-bit multipliers can deliver PDAP gains up to 7.1 ×, 8.3 ×, and 5.0 ×, respectively.

Keywords— Approximate computing, approximate compressor, error-resilient application, multiplier, power-delay-area product

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Block Diagram

Learning Outcomes

· Enhanced Performance Metrics

· Reduced Power Consumption

· Area Optimization

· Improved System Throughput

· Error Resilience Validation

· Scalable and Adaptable Designs

· Real-World Application Implementations

Demo Video

https://youtu.be/2giI_iKT1EI?si=8wBCApB4C0i6_9J4

Front End Domains

Arithmetic Core
Communications
DSP Core
FPGA

Back End Domains

Core Memories
Low Power VLSI
Transistor Logic
Nano Technology

Tools

Xilinx ISE
FPGA
Cadence EDA
Xilinx Vivado

Others

Matlab Interfacing