FPGA Based Low Power Approximate Hybrid Parallel Prefix Adders with Less Area

Approximate parallel prefix adders (AxPPA) are a type of circuit that can perform addition operations on binary numbers with high speed and low power consumption with less area. These circuits provide approximate results, which means that they sacrifice accuracy for efficiency. This trade off makes them ideal for use in applications where speed is more important than precision. In recent years, there has been a growing interest in the development of these circuits, as they have the potential to revolutionize the field of digital signal processing. In this paper, an overview of approximate parallel prefix adders and methods for reducing the error rate of AxPPA by modification of the architectures for the following PPA adders: approximate Knowles (AxKWPPA), and Sklansky (AxSKPPA). The proposed adders aim at reduce the area, delay and Power delay Product. These proposed adders designed, simulated and implemented with Verilog HDL (IEEE 1364-2005), Xilinx Vivado software tool (Xilinx Vivado2018.1) and Digilent Artix7 FPGA board (XC7A35TICSG324-1L) respectively. The proposed adders verified by implementing them in FPGA In the Loop for the image enhancement and contrast applications.