Floating Point Complex Multiplier Using Urdhva-Tiryakbhyam Sutra
Objective
This paper presents a high-speed floating point complex multiplier based on the Vedic mathematics principle of Urdhva-Tiryakbhyam Sutra. Complex multiplication is a core operation in digital signal processing, OFDM communication systems, and FPGA-based computing. The proposed architecture implements IEEE 754 single-precision floating point complex multiplication using Vedic multiplier cores for mantissa computation, enabling fast partial product generation with reduced logic depth
Abstract
This paper presents a high-speed floating point complex multiplier based on the Vedic mathematics principle of Urdhva-Tiryakbhyam Sutra. Complex multiplication is a core operation in digital signal processing, OFDM communication systems, and FPGA-based computing. The proposed architecture implements IEEE 754 single-precision floating point complex multiplication using Vedic multiplier cores for mantissa computation, enabling fast partial product generation with reduced logic depth. The design is modeled in Verilog HDL, synthesized on an FPGA platform using Xilinx Vivado, and evaluated against conventional multiplier designs. Results demonstrate significant improvements in critical path delay, operating frequency, and resource utilization, making the design suitable for high-throughput DSP and FFT applications.
Keywords: Floating Point Multiplier, Complex Multiplier, Urdhva-Tiryakbhyam, Vedic Mathematics, FPGA, DSP, IEEE 754
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Block Diagram
Specifications
Software Requirements
• Xilinx Vivado / ISE
• Verilog HDL / ModelSim
Hardware Requirements
• Xilinx FPGA (Spartan / Virtex)
• Logic Analyzer
Learning Outcomes
• Vedic Mathematics in VLSI Design
• IEEE 754 Floating Point Arithmetic
• FPGA Resource Optimization
• High-Speed Multiplier Architecture
• Digital Communication Hardware Design
Paper Publishing
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