Feed Forward-Cut Set-free Pipe Lined Multiply–Accumulate Unit for the Machine Learning Accelerator

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVREFE19_49

Objective

In the proposed scheme, the number of flip-flops in a pipeline can be reduced by relaxing the feed forward-cut set constraint, thanks to the unique characteristic of the machine learning algorithm.

Abstract

Multiply-accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. A large number of flip-flops are often required to meet the feedforward-cutset rule. Based on the observation that this rule can be relaxed in machine learning applications, we propose a pipelining method that eliminates some of the flip-flops selectively. The simulation results show that the proposed MAC unit achieved a 20% energy saving and a 20% area reduction compared with the conventional pipelined MAC.

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