Feed Forward-Cut Set-free Pipe Lined Multiply–Accumulate Unit for the Machine Learning Accelerator

Also Available Domains DSP Core|Xilinx Vivado

Project Code :TVPGTO544

Objective

In the proposed scheme, the number of flip-flops in a pipeline can be reduced by relaxing the feed forward-cut set constraint, thanks to the unique characteristic of the machine learning algorithm.

Abstract

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Specifications

Software Requirements:

Tanner EDA
Technology files:180nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing