Feed Forward-Cut Set-free Pipe Lined Multiply–Accumulate Unit for the Machine Learning Accelerator
Also Available Domains DSP Core|Xilinx ISE
Project Code :TVPGTO543
Objective
In the proposed scheme, the number of flip-flops in a pipeline can be reduced by relaxing the feed forward-cut set constraint, thanks to the unique characteristic of the machine learning algorithm.
Specifications
Software Requirements:
- Xilinx Vivado
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Related Topics
Paper Publishing
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