Fault Tolerant Reversible Full Adder Design Using Gate Diffusion Input

Also Available Domains Transistor Logic|H-Spice|Cadence EDA|LT-Spice

Project Code :TVMATO944

Abstract

GDI technique allows minimization of area and power consumption of digital circuits. The reversible gate preserves same parity between output and input vectors is called fault tolerant but the dimension should be 3. In this design, Peres Gate is designed using Gate Diffusion Input using 8 transistors. The proposed new Peres Gate is used to design full adder with power efficient and fault tolerant. In this work power consumption is reduced and the minimum power consumption achieved for supply voltage 1V and the total area is reduced as comparing with the previous works .The schematic is designed in Tanner EDA tool.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Specifications

Software & Hardware Requirements

· Tanner EDA.

Learning Outcomes

Learning Outcomes:

Introduction to Adders concept.

Types of functional blocks used in full-adder.
Limitations & Applications.

Introduction to GDI concept.

Knowledge on different voltage levels as an output.
Knowledge on GDI based logic circuits

Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for current starved ring oscillators.
How to design Proposed circuits of current starved ring oscillators.
Introduction to Analog Electronics
Importance of memristor
Scope of memristor in memory devices and IOT applications.
Applications in Real time.

Tanner EDA tool for design and simulation
Solution providing for real time problems

Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation skills
Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice