Fast Supersingular Isogeny DiffieHellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier

Also Available Domains Arithmetic Core|Xilinx ISE

Project Code :TVPGTO876

Objective

The main objective of this paper is to design the Pipelined Montgomery multiplier in order to minimize the latency of multiplier is far shorter.

Abstract

We present a pipelined Montgomery multiplier tailored for SIKE primes. The latency of this multiplier is far shorter than that of the previous work while its frequency competes with the highest-rated ones. The implementation results on a Virtex-7 FPGA show that this multiplier improves the time, the area-time product (AT), and the throughput of computing modular multiplication by at least 2.30, 1.60, and 1.36 times over SIKE primes respectively. We have also developed a CPU-like architecture to perform SIDH and SIKE using several instances of our modular multiplier. Using four multipliers on a Virtex-7 FPGA, the encapsulation and the decapsulation of SIKE can be performed at least 1.45 times faster while improving the AT by at least 1.35 times over all SIKE primes. The synthesis and simulation of the proposed designs can be implemented using Xilinx Vivado2018.3.

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Block Diagram

Specifications

Software Requirements:

·         Xilinx Vivado2018.3 Tool.

·         HDL: Verilog.

Hardware Requirements:

·         Microsoft® Windows XP.

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.

·         512 MB RAM.

·         100 MB of available disk space.

Learning Outcomes

  • Basics of Digital Electronics.
  • Concept of multiplier.
  • Difference between SIDH and SIKE.
  • Introduction to Verilog Coding.
  • Different modeling styles in Verilog.

o   Data Flow modeling.

o   Structural modeling.

o   Behavioral modeling.

o   Mixed level modeling.

  • Introduction to cryptographic systems.
  • About RCA and ECC cryptography.
  • Knowledge on pipelined Montgomery multiplier.
  • Knowledge on key encapsulation.
  • About approximation computing.
  • Applications in real time
  •  Xilinx Vivado2018.3 for design and simulation.
  • Generation of Netlist.
  • Solution providing for real time problems.
  •  Project Development Skills:

o   Problem Analysis Skills.

o   Problem Solving Skills.

o   Logical Skills.

o   Designing Skills.

o   Testing Skills.

o   Debugging Skills.

o   Presentation Skills.

o Thesis Writing Skills.

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