Fast Energy Efficient Radix-16 Sequential Multiplier

We propose a new sequential multiplier design that generates the radix-16 partial products (e.g., 𝑃) as two high (𝐻) and low (𝐿) components, such that 𝑃=4𝐻+𝐿, 𝐻,∈{0,1,2,3}×𝑋, where 𝑋 denotes the multiplicand. The required hard 3𝑋 multiple is generated in a preliminary cycle to the advantage of reducing the cycle time of the main iteration. Two radix-16 carry-save adders are used to generate the radix-16 accumulated partial product. The synthesis results show improved latency, power dissipation, and energy consumption over the previous relevant designs at the cost of additional silicon area, while however, the energy-area product is also lowered.