Also Available Domains Communications|FPGA|Xilinx Vivado
The main theme of this work is to protect the memories against soft errors by reducing the minimal path delay. This technique uses a single-bit parity for fault detection & the binary-encoded TCAM table maintained in SRAM-based TCAMs for update purposes.
In this project, a low-cost, low-response time and easy for integration technique for the protection of SRAM-enabled TCAMs without compromising the search performance is presented. The error detection is carried out in a simple way using single-bit parity checking at a minimal delay and logic overhead. The proposed error-correction technique exploits the redundant binary-encoded TCAM table maintained in SRAM-based TCAM solutions for update purposes to correct soft errors.
It maintains a high search performance while the proposed error correction mechanism is carried out in the background, allowing search operations to be performed simultaneously.
The proposed error-correction technique has a low response time, ensuring a faultless TCAM design for lookups, during the entire processing time. This design is synthesized and simulated using Xilinx ISE 14.7
Keywords: Field Programmable Gate Array (FPGA), soft errors, Static Random Access Memory (SRAM), Ternary Content Addressable Memory (TCAM)
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