Enhancing Security in FPGA-Based RISC-V Implementations Using Boolean Masking Techniques

The paper "A Guided Finite-State-Machine for IP Protection of Sequential Circuits" introduces a novel approach to protect Intellectual Property (IP) in sequential circuits. The researchers propose using a Finite State Machine (FSM) guided by a Cellular Automaton (CA) to implement a watermarking strategy. This method enables easy in-field authentication without compromising the security of the design. The authors demonstrate their approach using a UART receiver implemented in Verilog on an FPGA using Vivado. The UART receiver receives keys from a Putty terminal to decrypt the sequential circuit. UART receivers are essential components in serial communication systems, facilitating data transmission between devices at a relatively slow pace. In the context of this paper, the UART receiver serves as the interface between the user and the protected circuit. The keys received are utilized to control the state transitions of the FSM, which subsequently controls the decryption process of the sequential circuit. This method of IP protection is particularly effective for sequential circuits, which are common in hardware designs. By employing a FSM guided by a CA, the authors provide a secure and efficient solution for watermarking these circuits. This approach offers the added benefit of practical applicability, demonstrating the effectiveness of FSMs and CAs in real-world scenarios. By integrating this method with a UART receiver implemented on an FPGA using Vivado, the authors further enhance the practical utility of their approach. The UART receiver serves as the key interface between the user and the protected circuit, receiving keys to decrypt the sequential circuit. This setup provides a robust solution for protecting IP in hardware designs, contributing significantly to the field of IP protection.

Keywords: Universal Asynchronous Receiver Transmitter (UART), Field-programmable gate array (FPGA), Intellectual Property (IP), Finite State Machine (FSM).