Enhancing Performance of Floating Point Units Using Parallel Prefix Adders
Objective
The objective of this project is to design and implement an optimized Floating Point Unit (FPU) using parallel prefix adders to enhance computational speed and efficiency. It focuses on improving arithmetic operation performance by integrating high-speed adder architectures into the FPU design. Different parallel prefix structures such as Kogge-Stone and Brent-Kung adders will be analyzed and compared based on delay, area, and power consumption. Simulation and verification will be performed to validate the functional accuracy and performance improvements. The overall goal is to develop a high-performance, low-latency FPU suitable for advanced digital and signal processing applications
Abstract
Abstract:
This paper aims to investigate whether replacing behavioral adders with structural Parallel Prefix Adder architectures, such as Kogge-Stone, Ladner-Fischer, Brent-Kung, and Han-Carlson, can improve circuit performance. This investigation is performed on Floating Point Units (FPU) and specifically for an Addition-Subtraction, a Multiplication, a Multiplication and Accumulation, a Reciprocal, a Division, a Square root, and an Inverse Square root circuit, but can also be used in other circuits. Several behavioral adders are used in these circuits or IP blocks where these adders are typically implemented by the synthesis tools. Although several adder architectures have appeared in literature, the suitability of these adders for a specific FPU circuit cannot be determined in a straightforward manner as demonstrated in this paper.NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements
- Xilinx Vivado Design Suite (2020.2 or later)
- Verilog HDL for RTL design and implementation
- Vivado Simulator (XSIM) for functional and timing verification
- MATLAB (optional) for GPR data preprocessing, noise modeling, and result validation
Hardware Requirements
- Microsoft® Windows 10 / Windows 11 (64-bit)
- Intel® Core™ i5 / i7 Processor or equivalent
- Minimum 8 GB RAM
- Minimum 500 MB free disk space
Learning Outcomes
Understanding of floating-point arithmetic and multiplier design.
Knowledge of different adder architectures (ripple-carry, CLA, PPA) and their impact on latency.
Hands-on experience in FPGA-based design and hardware optimization.
Ability to analyze trade-offs between speed, area, and power in digital circuits.
Insight into implementing high-speed arithmetic operations for DSP and scientific computing applications.
Paper Publishing
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