Energy-Efficient Single-Ended Read Write 10T Near Threshold SRAM
Objective
The proposed SE10T improves read stability and write stability with the help of a built-in read-assist scheme and a power-gating technique, respectively, and reduces power/energy consumption by using single-ended read/write operation and stacking of transistors in the cell core.
Abstract
The increasing demand for low-power and energy-efficient computing systems has driven the development of near-threshold voltage (NTV) operation as a promising technique to mitigate power consumption in SRAM (Static Random-Access Memory) cells. This paper presents a novel single-ended read/write 10T SRAM cell design optimized for near-threshold operation, targeting energy-efficient applications in battery-constrained devices and energy-harvesting systems.
Through extensive simulations and evaluations, we demonstrate that the proposed 10T NTV SRAM cell achieves substantial improvements in energy efficiency compared to conventional SRAM designs. It exhibits superior read and write access times, making it suitable for a wide range of low-power applications, including IoT devices, wearable electronics, and energy-constrained sensor nodes.
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Block Diagram
Specifications
Software Requirements:
· Tool: LT-spice
· Technology: 32nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
· Introduction to digital & analog electronics
· Knowledge of MOSFETs
o Operation and characteristics of PMOS & NMOS
o Knowledge on Threshold voltages
· Basics of SRAM
o Operation of SRAM
o SNM and Power Analysis
· Knowledge on Tool Learning
Scope of SRAM in Real time.
Paper Publishing
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