Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators

Also Available Domains Arithmetic Core|Xilinx Vivado|Xilinx ISE

Project Code :TVPGFE91

Objective

The main objective of this work is to reduce the critical path delay for unsigned multipliers. In this proposed work, partial product encoding technique reduces the length of the carry chain in each partial product to further reduce the critical path of the multiplier

Abstract

In this project, a novel architecture for Booth multiplier is implemented. By using 6-input LUTs and associated fast carry chains of modern FPGAs, we present an architecture for signed multipliers that provides better performance than state-of-the-art designs. The proposed partial product encoding technique reduces the length of the carry chain in each partial product to further reduce the critical path of the multiplier. FPGA-based designs that exist are largely limited to unsigned numbers, which require extra circuits to support signed operations. To overcome these limitations for the FPGA-based implementations of applications utilizing signed numbers, this project presents an area-optimized, low-latency and energy-efficient architecture for accurate signed multiplier.

Keywords: Energy-Efficient applications, Signed multipliers, FPGA-based designs

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.