Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
Also Available Domains FPGA|Arithmetic Core|Xilinx ISE
Objective
The main objective of this work is to reduce the critical path delay for unsigned multipliers. In this proposed work, partial product encoding technique reduces the length of the carry chain in each partial product to further reduce the critical path of the multiplier
Abstract
In this project, a novel architecture for Booth multiplier is implemented. By using 6-input LUTs and associated fast carry chains of modern FPGAs, we present an architecture for signed multipliers that provides better performance than state-of-the-art designs.
The proposed partial product encoding technique reduces the length of the carry chain in each partial product to further reduce the critical path of the multiplier. FPGA-based designs that exist are largely limited to unsigned numbers, which require extra circuits to support signed operations.
To overcome these limitations for the FPGA-based implementations of applications utilizing signed numbers, this project presents an area-optimized, low-latency and energy-efficient architecture for accurate signed multiplier. The effectiveness of the proposed design is synthesized and simulated using Xilinx Vivado software.
Keywords: Energy-Efficient applications, Signed multipliers, FPGA-based designs
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx Vivado
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding.
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Introduction to Multipliers
- Signed Multipliers
- Unsigned multipliers
- Concept of Low latency
- How Low Latency can be achieved
- Role of Low latency signed multipliers in neural network applications
- Drawbacks of unsigned multipliers
- Design of signed multipliers for neural networks
- How to achieve high speed, Low power and Area efficiency?
- Scope of low latency signed multipliers in today’s world
- Applications in real time
- Xilinx Vivado for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Paper Publishing
Request Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
