Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
Also Available Domains FPGA|Arithmetic Core|Xilinx Vivado
Objective
The main objective of this work is to reduce the critical path delay for unsigned multipliers. In this proposed work, partial product encoding technique reduces the length of the carry chain in each partial product to further reduce the critical path of the multiplier
Abstract
In this project, an efficient scheme is presented to correct limited magnitude errors on multilevel cell memories. The proposed scheme combines the use of a low redundancy SECDAEC code in the two lowest bits of the cell with IP bits to correct up to magnitude-3 symmetric errors. The SEC-DAEC code is used to locate the cell in error and correct errors on some bits.
The IP is used to identify the error pattern on the remaining bits. The proposed IP-DAEC scheme provides a simple implementation that achieves a low delay with a reduced number of parity bits.
The proposed scheme has been compared to existing schemes that have similar capability showing an advantage of memory redundancy, as well as a lower encoder/decoder overhead in most cases. The synthesis and simulation results are carried out using Xilinx ISE 14.7
Keywords: Error Correction Codes, Multilevel cell memories, limited magnitude errors, SEC-DAEC codes
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx ISE 14.7
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding.
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Introduction to Multipliers
- Signed Multipliers
- Unsigned multipliers
- Concept of Low latency
- How Low Latency can be achieved
- Role of Low latency signed multipliers in neural network applications
- Drawbacks of unsigned multipliers
- Design of signed multipliers for neural networks
- How to achieve high speed, Low power and Area efficiency?
- Scope of low latency signed multipliers in today’s world
- Applications in real time
- Xilinx ISE 14.7 for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Paper Publishing
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