Energy and Error Analysis Framework for Approximate Computing in Mobile Applications

Also Available Domains Tanner EDA|Cadence EDA

Project Code :TVPGBE56

Objective

In this proposed work three novel energy, delay and area-efficient full-swing hybrid CMOS adders were designed. The proposed adders are named approximate hybrid adders (AHA1, AHA2, AHA3), with a numeral at the end for the different designs

Abstract

In this project, three energy-efﬁcient approximate hybrid CMOS full-adders with varying levels of inaccuracies are proposed. Approximate circuits have conventionally been used in image/video processing applications, which are mostly limited to 8-bits. It is observed that in approximate adders where carry is approximated with 2-bit approximation in LSB, the absolute average error in image processing applications is ∼ 3. However, in mobile applications, approximation in carry can lead to an overﬂow.

Hence, approximate adders with carry approximation are not suitable for mobile computing. The adder designs are implemented in 45nm technology using Cadence Virtuoso. Compared to existing approximate adders, the proposed adders consume lesser energy and have lesser energy delay product.

Keywords: Approximate computing, approximate adder, hybrid CMOS Logic.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Tanner EDA/ Cadence Virtuoso
Technology files:45nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction to approximate computing
Drawbacks of using Exact computing error tolerant applications
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for approximate computing circuits
How to design low power, high speed area efficient transistor level circuits?
Scope of Approximate Computing in today’s world
Applications in real time
Tanner EDA/Cadence virtuoso tool for design and simulation
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing