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The main objective of this paper is to present an optimized architecture of a 2-bit square calculator using vedic sutra based on E-shaped XOR gate and majority gate.
Vedic mathematics is now being realized to have a large potential in recent times which can be used to design digital circuits using the Vedic formulas. Vedic mathematics is a new trend in quantum-dot cellular automata (QCA) technology. However, an efficient coplanar design and a complete performance analysis are still desired. This brief presents the coplanar QCA architecture of a 2-bits square calculator (proposed design-1 or PD1) using the Vedic sutra ‘Urdhva Tiryagbhyam’. Furthermore, based on the E-shaped XOR gate and majority gate (MV) an optimized architecture (proposed design-2 or PD2) is presented. The PD2 architecture exhibits notable improvement compared to the previous architecture. It is worth mentioning that the comprehensive performance analyses are carried out using the QCADESINER.
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Software Requirements:
· QCA Designer tool
· HDL: Verilog.
Hardware Requirements:
o Microsoft® Windows XP.
o Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
o 512 MB RAM.
o 100 MB of available disk space.
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills