In this paper, design of three different Array, Vedic and booth multipliers are presented, one by using ripple carry adder (RCA),carry select adder (CSLA) and ling adder’s logic for addition of partial product terms in partial product lines.
In this paper, design of three different Array, Vedic and booth multipliers are presented, one by using ripple carry adder (RCA),carry select adder (CSLA) and ling adder’s logic for addition of partial product terms in partial product lines. The multipliers presented in this paper were all modeled using VERILOG HDL for 32-bit unsigned data. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between conventional multiplier designs.
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Software Requirements:
· Xilinx Vivado2018.3 Tool/Xilinx ISE14.7 suite.
· HDL: Verilog.
Hardware Requirements:
· Microsoft® Windows XP.
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
· 512 MB RAM.
100 MB of available disk space.
o Data Flow modeling.
o Structural modeling.
o Behavioral modeling.
o Mixed level modeling.
o Problem Analysis Skills.
o Problem Solving Skills.
o Logical Skills.
o Designing Skills.
o Testing Skills.
o Debugging Skills.
o Presentation Skills.
o Thesis Writing Skills.