Efficient Design of Vedic Square Calculator Using Quantum Dot Cellular Automata QCA

Abstract:

Vedic mathematics is now being realized to have a large potential in recent times which can be used to design digital circuits using the Vedic formulas. Vedic mathematics is a new trend in quantum-dot cellular automata (QCA) technology. However, an efficient coplanar design and a complete performance analysis are still desired. This brief presents the coplanar QCA architecture of a 2-bits square calculator (proposed design-1 or PD1) using the Vedic sutra ‘Urdhva Tiryagbhyam’. Furthermore, based on the E-shaped XOR gate and majority gate (MV) an optimized architecture (proposed design-2 or PD2) is presented. The PD2 architecture exhibits notable improvement compared to the previous architecture. The proposed PD2 requires 17%, 53%, and 25% fewer cells, smaller areas, and lower latency, respectively. Likewise, the extended design for 4-bit architecture (proposed design-3 or PD3) achieves 67%, 63%, and 62% superiority in cell count, covered area, and latency, respectively. Compare to the best previous design, the area-delay, QCA-specific, and energy-delay costs for PD2 (PD3) are lower by a factor of ∼10 (∼30), ∼71 (∼33), and ∼64 (∼83), respectively. Moreover, there is an improvement in terms of power dissipation as the QCA-based design PD2 (PD3) dissipates 1.41×10−6 mW (11.82×10−6 mW), whereas the similar type CMOS-based designs dissipate 2.29×10−2 mW (48×10−2 mW), respectively. It is worth mentioning that the comprehensive performance analyses are carried out using the QCA Designer, QCA Designer-E tools.

Keywords: Multipliers, QCA circuits, QCA Designer, QCA Designer-E, square calculator, Vedic mathematics.