Abstract:

In this project, Power gating is commonly used to reduce leakage current in SRAM memories; leakage current has a large impact on SRAM energy consumption. We first focus on power gating FinFET SRAMs and then evaluate three techniques to reduce the leakage power and energy-delay product (EDP) of six- and eight transistor (6T, 8T) FinFET SRAM cells. We compare the EDP savings obtained using (1) power gating FinFETs, (2) near threshold operation and alternative SRAM cells with shorted gate (SG) and low power (LP) configured FinFETs; LP-configuration reverse-biases a FinFET’s back gate and reduces leakage current by up to 97%. SRAM cells with higher leakage benefit the most from power gating since they see the largest reductions in leakage current. Sharing power gating transistors among multiple SRAM cells can lead to more leakage current savings.