DPL-Based Novel Time Equalized CMOS Ternary-to-Binary Converter

Also Available Domains Cadence EDA

Project Code :TVMABE69

Objective

The main theme of this work is to convert the 3-valued ternary input into a two-valued binary output. This circuit was designed with Double Pass transistor Logic (DPL) by using this logic design power and power delay product will be reduced.

Abstract

In this project, a novel 3-step-strategy to convert Ternary-input into Binary-output using Double Pass-transistor Logic (DPL) is implemented. Radix-3 (Ternary) logic has been receiving renewed attention as a feasible alternative to conventional Radix-2 system in processor-design and multi-valued logic-design due to computational-ease, speed and reduced interconnect. Since the real world is binary, the ternary-processing stage must be appended with a ternary-to-binary converter.

Keywords: Ternary to Binary Converter (TBC), Double Pass-transistor Logic (DPL), Ternary Logic.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Tanner EDA/ Cadence Virtuoso
Technology files:180nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction to Ternary to binary converters
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for Ternary to binary converters
Knowledge on DPL Logic
Transistor level design using DPL Logic
How to design low power, high speed area efficient transistor level circuits?
Scope of Ternary converters in today’s world
Applications in real time
Tanner EDA/ Cadence EDA for design and simulation
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice